For
Tube-amp builders who want a real Studio: design any tube regulator from spec, simulate, diagnose and export.
You will learn
  • Compare every tube-only regulator topology on a shared bench
  • Master cold-cathode VR physics, stacking and ballast sizing
  • Design series + error-amp regulators with predictable Zout, ripple and stability
  • Diagnose live faults (oscillation, sag, hum, no-strike) with the interactive assistant
  • Export Markdown reports + SPICE netlists wired to Ampera's Koren tube models
Before you start
Power supply & rectification
Time & level
45 minAdvanced

Stability, compensation, real loads

4 minPrev
Chapter 8 / 84 min

Stability, compensation, real loads

Phase margin, the C_load pole, R_iso, and how to read a step response.

Every loop has poles. A regulator typically shows three: the dominant pole p1 from the error-amp anode load × Miller capacitance, a parasitic p2 from layout and tube interelectrode caps, and p3 from whatever capacitance you hang on the output node. The sum of their phase lags at the crossover fc sets the phase margin.

ConceptPhase margin reading
  • ≥ 60° — clean step response, no overshoot, settles in 5 / fc.
  • 30°–60° — 5–25 % overshoot, visible ringing.
  • < 30° — heavy ringing, on the edge of oscillation.
  • ≤ 0° — oscillates.
ConceptThe C_load pole is the killer

A 47 µF cap on Vout + an open-loop Rout of 70 Ω puts p3 at ~48 Hz. Inside the loop band-edge. Phase margin collapses; the regulator rings or sings at startup.

ConceptR_iso to the rescue

Insert a small series resistor Riso between Rout and Cload. The loop now sees Ceff = Cload × Rout / (Rout + Riso), which pushes p3 up out of the loop band. 22–47 Ω usually recovers 30–40° of margin at the cost of 1–2 V of dropout.

WarningDon't trust simulation alone
Phase margin sims ignore the parasitic that'll kill you: lead inductance, layout coupling, heater-cathode coupling capacitance. Always test with a real load step on the bench, scope on Vout, and confirm the overshoot matches the predicted figure within 50 %.
Calc · stability
Open →
Loop stability
Three sliders — Aol, Cload, Riso — read out phase margin in degrees, crossover fc, and predicted step-response overshoot percentage.
Lab · stability-dashboard
Run →
Stability dashboard
Three synced plots: Bode (gain + phase), pole-zero in the complex plane, and step response. Move sliders, watch every view update together.
Check yourself
Your loop has 60° phase margin at 5 kHz crossover. You add a 100 µF output cap with no R_iso. What happens?
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