Stability, compensation, real loads
Stability, compensation, real loads
Phase margin, the C_load pole, R_iso, and how to read a step response.
Every loop has poles. A regulator typically shows three: the dominant pole p1 from the error-amp anode load × Miller capacitance, a parasitic p2 from layout and tube interelectrode caps, and p3 from whatever capacitance you hang on the output node. The sum of their phase lags at the crossover fc sets the phase margin.
- ≥ 60° — clean step response, no overshoot, settles in 5 / fc.
- 30°–60° — 5–25 % overshoot, visible ringing.
- < 30° — heavy ringing, on the edge of oscillation.
- ≤ 0° — oscillates.
A 47 µF cap on Vout + an open-loop Rout of 70 Ω puts p3 at ~48 Hz. Inside the loop band-edge. Phase margin collapses; the regulator rings or sings at startup.
Insert a small series resistor Riso between Rout and Cload. The loop now sees Ceff = Cload × Rout / (Rout + Riso), which pushes p3 up out of the loop band. 22–47 Ω usually recovers 30–40° of margin at the cost of 1–2 V of dropout.